/**
 * @copyright 2018 indie Semiconductor
 *
 * This file is proprietary to indie Semiconductor.
 * All rights reserved. Reproduction or distribution, in whole
 * or in part, is forbidden except by express written permission
 * of indie Semiconductor.
 *
 * @file ioctrla_sfr.h
 */

#ifndef __IOCTRLA_SFR_H__
#define __IOCTRLA_SFR_H__

#include <stdint.h>

/* -------  Start of section using anonymous unions and disabling warnings  ------- */
#if   defined (__CC_ARM)
  #pragma push
  #pragma anon_unions
#elif defined (__ICCARM__)
  #pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic push
  #pragma clang diagnostic ignored "-Wc11-extensions"
  #pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning 586
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#else
  #warning Not supported compiler type
#endif


typedef union {
    struct {
      uint8_t  HWMODE                  :  1; /*!< Pin  hardware mode */
      uint8_t                          :  1; /*   (reserved) */
      uint8_t  RDENA                   :  1; /*!< Pin  read enable */
      uint8_t  PUENA                   :  1; /*!< Pin  pullup enable */
      uint8_t  PDENA                   :  1; /*!< Pin  pulldown enable */
      uint8_t                          :  3; /*   (reserved) */
    };
    uint8_t byte;
}GPIO_REG_t;

/**
 * @brief A structure to represent Special Function Registers for IOCTRLA.
 */
typedef struct {

//  union {
//    struct {
//      uint8_t  HWMODE0                  :  1; /*!< Pin 0 hardware mode */
//      uint8_t                           :  1; /*   (reserved) */
//      uint8_t  RDENA0                   :  1; /*!< Pin 0 read enable */
//      uint8_t  PUENA0                   :  1; /*!< Pin 0 pullup enable */
//      uint8_t  PDENA0                   :  1; /*!< Pin 0 pulldown enable */
//      uint8_t                           :  3; /*   (reserved) */
//      uint8_t  HWMODE1                  :  1; /*!< Pin 1 hardware mode */
//      uint8_t                           :  1; /*   (reserved) */
//      uint8_t  RDENA1                   :  1; /*!< Pin 1 read enable */
//      uint8_t  PUENA1                   :  1; /*!< Pin 1 pullup enable */
//      uint8_t  PDENA1                   :  1; /*!< Pin 1 pulldown enable */
//      uint8_t                           :  3; /*   (reserved) */
//      uint8_t  HWMODE2                  :  1; /*!< Pin 2 hardware mode */
//      uint8_t                           :  1; /*   (reserved) */
//      uint8_t  RDENA2                   :  1; /*!< Pin 2 read enable */
//      uint8_t  PUENA2                   :  1; /*!< Pin 2 pullup enable */
//      uint8_t  PDENA2                   :  1; /*!< Pin 2 pulldown enable */
//      uint8_t                           :  3; /*   (reserved) */
//      uint8_t  HWMODE3                  :  1; /*!< Pin 3 hardware mode */
//      uint8_t                           :  1; /*   (reserved) */
//      uint8_t  RDENA3                   :  1; /*!< Pin 3 read enable */
//      uint8_t  PUENA3                   :  1; /*!< Pin 3 pullup enable */
//      uint8_t  PDENA3                   :  1; /*!< Pin 3 pulldown enable */
//      uint8_t                           :  3; /*   (reserved) */
//    };
//    uint32_t WORD;
//  } GPAP03; /* +0x000 */
  GPIO_REG_t GPIO[4];

  union {
    struct {
      uint8_t                           :  2; /*   (reserved) */
      uint8_t  RDENA4                   :  1; /*!< Pin 4 read enable */
      uint8_t  PUENA4                   :  1; /*!< Pin 4 pullup enable */
      uint8_t  PDENA4                   :  1; /*!< Pin 4 pulldown enable */
      uint8_t                           :  3; /*   (reserved) */
      uint32_t                          : 24; /*   (reserved) */
    };
    uint32_t WORD;
  } GPAP4; /* +0x004 */

  union {
    struct {
      uint8_t  RE                       :  1; /*!< Uart Read Enable */
      uint8_t  OE                       :  1; /*!< Uart Output Enable */
      uint8_t                           :  6; /*   (reserved) */
      uint8_t  RXPOL                    :  1; /*!< Uart RXD Polarity */
      uint8_t  TXPOL                    :  1; /*!< Uart TXD Polarity */
      uint8_t                           :  6; /*   (reserved) */
      uint16_t                          : 16; /*   (reserved) */
    };
    uint32_t WORD;
  } UART; /* +0x008 */

  union {// Lin Slave
    struct {
      uint8_t  HWMODE                   :  1; /*!< Enable LIN1 HardWare Mode */
      uint8_t  RXENA                    :  1; /*!< LIN1 receive enable in non hardware mode */
      uint8_t                           :  2; /*   (reserved) */
      uint8_t  SPU30K                   :  1; /*!< LIN1 Slave Pullup Enable */
      uint8_t  MPU1K                    :  1; /*!< LIN1 Master Pullup Enable */
      uint8_t  RXPOL                    :  1; /*!< LIN1 receive  polarity */
      uint8_t  TXPOL                    :  1; /*!< LIN1 transmit  polarity */
      uint8_t  FRCTXENA                 :  1; /*!< LIN1 Force transmit enable */
      uint8_t  FRCTXENAVAL              :  1; /*!< LIN1 Force transmit enable Value */
      uint8_t                           :  6; /*   (reserved) */
      uint8_t  RXD                      :  8; /*!< RX Data */
      uint8_t  TXD                      :  8; /*!< TX Data */
    };
    uint32_t WORD;
  } LIN1; /* +0x00C */

  union {// LIN master
    struct {
      uint8_t  HWMODE                   :  1; /*!< Enable LIN2 HardWare Mode */
      uint8_t  RXENA                    :  1; /*!< LIN2 receive enable */
      uint8_t                           :  2; /*   (reserved) */
      uint8_t  SPU30K                   :  1; /*!< LIN2 Slave Pullup Enable */
      uint8_t  MPU1K                    :  1; /*!< LIN2 Master Pullup Enable */
      uint8_t  RXPOL                    :  1; /*!< LIN2 receive  polarity */
      uint8_t  TXPOL                    :  1; /*!< LIN2 transmit  polarity */
      uint8_t  FRCTXENA                 :  1; /*!< LIN2 Force transmit enable */
      uint8_t  FRCTXENAVAL              :  1; /*!< LIN2 Force transmit enable Value */
      uint8_t                           :  6; /*   (reserved) */
      uint8_t  RXD                      :  8; /*!< RX Data */
      uint8_t  TXD                      :  8; /*!< TX Data */
    };
    uint32_t WORD;
  } LIN2; /* +0x010 */

  union {
    struct {
      uint8_t  M1S2                     :  8; /*!< LIN Master/Slave Port Select */
      uint8_t  BYPASS                   :  8; /*!< LIN Bypass Mode */
      uint16_t                          : 16; /*   (reserved) */
    };
    uint32_t WORD;
  } LINMUX; /* +0x014 */

  union {
    struct {
      uint8_t  BIAS1                    :  1; /*!< LIN1 Bias Enable */
      uint8_t  BIAS2                    :  1; /*!< LIN2 Bias Enable */
      uint8_t                           :  6; /*   (reserved) */
      uint32_t                          : 24; /*   (reserved) */
    };
    uint32_t WORD;
  } LINLP; /* +0x018 */

  uint32_t HWMODE;                            /*<! Hardware mode for 24 LEDs +0x01C */

  uint32_t DATA;                              /* +0x020 */

  uint8_t  ENA;                               /* +0x024 */
  uint8_t  _RESERVED_25[3];                   /* +0x025 */

  union {
    struct {
      uint8_t  TESTMUXSEL0              :  8;
      uint8_t  TESTMUXSEL1              :  8;
      uint8_t  TESTMUXSEL2              :  8;
      uint8_t                           :  8; /*   (reserved) */
    };
    uint32_t WORD;
  } TESTMUXSEL; /* +0x028 */

  union {
    struct {
      uint8_t  VBGENA                   :  1; /*!< Enable for the VBG trim mux */
      uint8_t  VBGINSEL                 :  1; /*!< Input Select for VBG trim mux */
      uint8_t                           :  6; /*   (reserved) */
      uint32_t                          : 24; /*   (reserved) */
    };
    uint32_t WORD;
  } TRIMMUX; /* +0x02C */

  union {
    struct {
      uint8_t  CLRGUARD                 :  8; /*!< Clear Guard */
      uint8_t  INSEL                    :  8; /*!< Analog test/trim Mux Input Select */
      uint8_t  OUTSEL                   :  8; /*!< Analog test/trim Mux Output Port Select */
      uint8_t  GUARD                    :  8; /*!< Guard against glitch during change of TESTMUX Select */
    };
    uint32_t WORD;
  } ANAMUX; /* +0x030 */

} IOCTRLA_SFRS_t;

/* --------  End of section using anonymous unions and disabling warnings  -------- */
#if   defined (__CC_ARM)
  #pragma pop
#elif defined (__ICCARM__)
  /* leave anonymous unions enabled */
#elif (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic pop
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning restore
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#else
  #warning Not supported compiler type
#endif

/**
 * @brief The starting address of IOCTRLA SFRS.
 */
#define IOCTRLA_SFRS ((__IO IOCTRLA_SFRS_t *)0x50012000)

#endif /* end of __IOCTRLA_SFR_H__ section */


